TSS

The TSS (Task State Segment) is a special segment describing a task, it’s thus present in the GDT, like others segment descriptor.

The goal of this segment is to describe all the task information such as all the registers, the IO permissions (to give a task rights for inb and outb operations), and the stack to be used when changing the privilege level.

The intel processor can use the TSS to do full hardware context switch, however it has been deprecated, and as such is not fully used. Still, a TSS is mandatory for a user space: it’s the only way to tell the processor which stack it should use when switching to kernel land.

The TSS format is as follow:

The ESPn and SSn are used when switching to ring level n, the processor will automatically use those. The other fields are only useful when using hardware task switching: those represent the state of all registers.

Because the TSS is a segment, it should be present in the GDT, the entry is as follow:

As you can see, it’s not very different from a data or code segment.

The last thing to do is to inform the processor about the entry in the GDT which contain the TSS. This is done by the instruction ltr which takes a segment selector in parameter:

movw $0x10, %ax
ltr %ax /* The second GDT entry describe the TSS */